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10 CH PLL
S5T8803A
INTRODUCTION
The S5T8803A is designed to select 10 channels of a cordless phone, whose frequency band is 46/49MHz. It has a reference frequency generator, programmable divider for Transmit and Receive section, and phase detector. 16-DIP-300A
FEATURES
* * * * * Able to select 10 Channels: S5T8803A (both transmit/receive) Include oscillation circuit with external x-tal (10.24MHz) 5KHz output for guard tone Unlock detector (phase difference more than 6.25us) Standby function for power saving 16-SOP-225
ORDERING INFORMATION
Device S5T8803A01-D0B0 S5T8803A01-S0B0 Package 16-DIP-300A 16-SOP-225 Operating Temperature -30C to +75C
1
S5T8803A
10 CH PLL
BLOCK DIAGRAM
VDD
VSS
15
12
+ VDD
OSCI
16 1 11
PHASE DETECTOR (Tx)
4
REFERENCE DIVIDER
F1
OSCO
PDT
PHASE DETECTOR (Rx)
13
PDR
TIF
9
PROGRAMMABLE DIVIDER (Tx)
PROGRAMMABLE DIVIDER (Rx)
14
+
RIF
DECODER
UNLOCK DETECTOR
10
LDT
3
SB
5
D0
6
D1
7
D2
8
2
D3 MODE
PIN CONFIGURATION
OSCO
1 2 3 4 S5T8803A 5 6 7 8
16 15 14 13 12 11 10 9
OSCI
MODE
VDD
SB
RIF
F1
PDR
D0
VSS PDT
D1
D2
LDT
D3
TIF
2
10 CH PLL
S5T8803A
PIN DESCRIPTION
Pin No 1 2 Symbol OSCO MODE Description This output generates the reference frequency when it is connected to Pin 16 with the external OSC, whose frequency is 10.24MHz. Base/Remote Unit Selection Pin. "High": Base Unit "Low" : Remote Unit Standby pin. This input controls Tx PLL for reducing the power dissipation "High": Normal operation "Low": Standby 5KHz output Channel selection pins The Combinations of these inputs select one channel among the 10 channels Input to programmable divider of Tx. AC coupling with VCO In case of a larger signal, It needs DC-coupling. Minimum input voltage is 0.1 Vrms Unlocked signal out pin (see output characteristics) Phase detector output for Tx. PDT detects the phase error from Tx PLL and its output is connected to the external low pass filter This pin is the negative supply of the IC. It is usually grounded Phase detector output for Rx. PDR detects the phase error from Rx PLL and its output is connected to the external low pass filter Input of programmable divider for Rx. AC coupling with VCO In case of a larger signal (standard CMOS logic), it needs DC coupling. Minimum input voltage is 0.1Vrms This pin is the positive supply of the IC Its reference is VSS, and normally + 3.0V ~ + 5.5V more positive than VSS X-TAL OSC connection pin This input generates the reference frequency when it is connected to pin 1 with the external OSC
3
SB
4 5, 6 7, 8 9 10 11
F1 D0, D1 D2, D3 TIF LDT PDT
12 13 14
VSS PDR RIF
15 16
VDD OSCI
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD VI PD TOPR TSTG Value -0.5 ~ +6.0 -0.3 ~ VDD + 0.5 350 -30 ~ + 75 -40 ~ + 125 Unit V V mW C C
3
S5T8803A
10 CH PLL
ELECTRICAL CHARACTERISTICS
(Ta = 25C, VDD = 5 V, unless otherwise specified) Characteristic Supply Voltage Input Voltage Symbol VDD VIH1 VIL1 VIH2 VIL2 fI1 Input Frequency fl2 fI3 VI(AMP)1 Input Amplitude VI(AMP)2 VI(AMP)3 Input Current IIH IIL Output Voltage VOH1 VOL1 VOH2 VOL2 Output OFF Leakage Current Standby Current ILKG1 ILKG2 ISB1 ISB2 Operating Current IDD1 IDD2 D0 - D3, SB D0 - D3, SB MODE MODE VTIF = 0.15Vrms VRIF = 0.15Vrms OSCIN = 0.3Vrms fTIF = 52MHz fRIF = 42MHz OSCIN = 11MHz VIN = VDD VIN = VSS PDT, RDR: IO = 0.5mA PDT, RDR : IO = 0.5mA LDT: IO = 1mA F1: IO = 1mA PDT, PDR : VO = VDD/VSS LDT: VO = VSS VDD = 3V (Note 2) VDD = 3V (Note 2) VDD = 3V (Note 1) VDD = 5V (Note 1) Test Conditions - Min. 3 0.7 VDD - 0.9 VDD - 10 30 5 0.1 0.1 0.3 - - VDD-1.0 - VDD-1.0 - - - - 3.5 - - Typ. - - - - - - - 10.24 - - - - - - - - - 0.01 - 1.0 4.0 2.0 6.0 Max. 5.5 VDD 0.3VDD VDD 0.1VDD 52 42 11 0.3VDD 0.3VDD 0.3VDD 40 40 - 1.0 - 1.0 1.0 5.0 2.0 - 3.0 7.0 Unit V V V V V MHz MHz MHz Vrms Vrms Vrms A A V V V V A A mA mA mA mA
NOTES: 1. OSC IN: 10.24MHz X-tal Connection TIF: 27MHz 150 mVrms RlF: 42MHz 150 mVrrns MODE: VDD, SB = VDD, others are opened 2. OSC IN: 10.24MHz X-tal Connection TlF: 27MHz 150rnVrms RIF: 42MHz 150mVrms MODE: VDD, SB = VSS, others are opened
Capacitor more than 2000pF should be connected between VDD & VSS
4
10 CH PLL
S5T8803A
OUTPUT CHARACTERISTICS
LOCK
tPD
tPD tPD : Phase Difference ( 6.25s ) VDD VSS VDD VSS
Reference Divider Programmable Divider LDT 2) UNLOCK Reference Divider Programmable Divider LDT 6.4ms
Floating VDD VSS VDD VSS VDD Floating
Figure 1.
5
S5T8803A
10 CH PLL
Channel & Frequency table to Base/Remote Input Data for S5T8803A (10-CH) BASE (MODE = 1)
INPUT D0 D1 D2 D3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 CH 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 fRX(MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.970 49.970 49.970 49.970 49.970 49.970 Rx (fREF = 5kHz) fVCO(MHz) 38.975 39.150 39.165 39.075 39.180 39.135 39.195 39.235 39.295 39.275 39.275 39.275 39.275 39.275 39.275 39.275 N 7795 7830 7833 7815 7836 7827 7839 7847 7859 7855 7855 7855 7855 7855 7855 7855 fTX(MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.970 46.970 46.970 46.970 46.970 46.970 Tx (fREF = 5kHz) fVCO(MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.970 46.970 46.970 46.970 46.970 46.970 N 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 9394 9394 9394 9394 9394 9394
REMOTE (MODE = 0)
INPUT D0 D1 D2 D3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 CH 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 fRX(MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.970 46.970 46.970 46.970 46.970 46.970 Rx (fREF = 5kHz) fVCO(MHz) 35.915 35.935 35.975 36.015 36.035 36.075 36.135 36.175 36.235 36.275 36.275 36.275 36.275 36.275 36.275 36.275 N 7183 7187 7195 7203 7207 7215 7227 7235 7247 7255 7555 7255 7255 7255 7255 7255 fRX(MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.970 49.970 49.970 49.970 49.970 49.970 Tx (fREF = 5kHz) fVCO(MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.970 49.970 49.970 49.970 49.970 49.970 N 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994 9994 9994 9994 9994 9994 9994
6
10 CH PLL
S5T8803A
APPLICATION CIRCUIT
ANT BPF 46.610MHz (R) 49.670MHz (B) 1st 10.695MHz MIX 39.915MHz 38.975MHz (B) 2nd MIX 10.24MHz 455KHz
BPF
49.670MHz (R) 46.610MHz (B)
(R) : REMOTE UNIT (B) : BASE UNIT
RX VCO
Tx VCO
VDD
to MICOM (Unlock Detect)
16
15
14
13
12
11
10
9
PROGRAMMABLE DIVIDER (Rx)
PHASE DETECTOR (Rx)
PHASE DETECTOR (Tx)
REF. DIVIDER
PROGRAMMABLE DIVIDER (Tx)
DECODER
1
X-TAL 10.24MHz VDD BASE REMOTE
2
3
4
5
6
7
8
to MICOM (D0, D1, D2, D3) 5.0KHz
VDD : TX PLL ENABLE VSS : TX PLL DISABLE
7
S5T8803A
10 CH PLL
NOTES
8

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